Search - alu verilog

[Other resource] alu_32_bit

Description: verilog 32-bit ALU-verilog 32-bit ALU
Platform: | Size: 2286 | Author: qwasqwas | Hits:

[Other resource] verilog

Description: 8bit alu use verilog hdl
Platform: | Size: 8752 | Author: 周微微 | Hits:

[Other resource] ALU

Description: 用verilog编写的32位alu部件，用于cpu制作
Platform: | Size: 3377 | Author: 胡豫陇 | Hits:

[Other resource] ALU

Description: 用verilog编写的4位ALU，由算术运算模块、逻辑运算模块、选择模块组成
Platform: | Size: 2793 | Author: 姚伟 | Hits:

[Other resource] ALU

Description: 用VERILOG实现ALU，实现各种算术运算，逻辑运算，移位运算等
Platform: | Size: 1725616 | Author: 刘自强 | Hits:

[Other resource] alu-div

Description: 用verilog HDL代码编写的快速除法器，比较有用
Platform: | Size: 15134 | Author: 徐芬 | Hits:

[Other resource] alu

Description: verilog编写的alu模块-Verilog modules prepared by the ALU
Platform: | Size: 1393 | Author: 刘陆陆 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Verilog_Example(wangjinming)

Description: 王金明老师讲述的100个Verilog代码示例，并附带有相关说明，Verilog初学者很好的入门资料！-Wang Jinming teacher described Verilog sample code 100, together with a related note, Verilog good introductory information for beginners!
Platform: | Size: 167936 | Author: 王鹏 | Hits:

[VHDL-FPGA-Verilog] alu181

Description: alu运算器vhdl代码，介绍了16中运算方法，可用于cpu的设计中-alu calculator VHDL code, introduction of 16 in computing methods, can be used for the design of cpu
Platform: | Size: 1024 | Author: 赵心 | Hits:

[Other] alu_Verilog

Description: It is the code for implementing the project titled "The Reconfigurable Instruction Cell Array(IEEE 2008)".
Platform: | Size: 5120 | Author: masth | Hits:

[VHDL-FPGA-Verilog] 8risc

Description: 8位RISC CPU,包括alu,count,machine-8 bit risc cpu
Platform: | Size: 3072 | Author: 刘成诚 | Hits:

[VHDL-FPGA-Verilog] myAddSub

Description: Verilog adder for alu develpment
Platform: | Size: 1024 | Author: ricardiito | Hits:

[VHDL-FPGA-Verilog] traffic_lights

Description: Verilog语言3个程序，包括4位二进制的BCD码加法器，ALU位片，交通信号灯。既有源码也有word文档说明。-Verilog language three procedures, including 4-bit binary code of the BCD adder, ALU-bit chip, traffic lights. Only source documents that have word.
Platform: | Size: 1596416 | Author: 郭函 | Hits:

[VHDL-FPGA-Verilog] alu

Description: alu for verilog it s simple
Platform: | Size: 1024 | Author: JunKim | Hits:

[VHDL-FPGA-Verilog] processor

Description: verilog program for alu
Platform: | Size: 8192 | Author: saiprasanth | Hits:

[VHDL-FPGA-Verilog] ALUALUcontrol

Description: 实现32位的ALU，使其能够支持基本的指令。用Verilog HDL语言或VHDL语言来编写，实现ALU及ALU控制器。 -To achieve 32-bit ALU, so that it can support the basic directives. With the Verilog HDL language or VHDL language to write, implement ALU and the ALU controller.
Platform: | Size: 1060864 | Author: 于伟 | Hits:

[VHDL-FPGA-Verilog] 5

Description: simple code based on verilog shifter , cla ,clg , ALU ,PC, decoder , tb_top
Platform: | Size: 16384 | Author: Tera | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[VHDL-FPGA-Verilog] Designs

Description: design files in verilog, alu, array mult, carry shift etc.
Platform: | Size: 37888 | Author: p2p_123 | Hits:

[VHDL-FPGA-Verilog] alu

Description: this is source code in verilog for arithmatic logic unit for RISC cpu
Platform: | Size: 63488 | Author: Harshit B J | Hits:

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[Other resource] alu_32_bit

[Other resource] verilog

[Other resource] ALU

[Other resource] ALU

[Other resource] ALU

[Other resource] alu-div

[Other resource] alu

[ARM-PowerPC-ColdFire-MIPS] Verilog_Example(wangjinming)

[VHDL-FPGA-Verilog] alu181

[Other] alu_Verilog

[VHDL-FPGA-Verilog] 8risc

[VHDL-FPGA-Verilog] myAddSub

[VHDL-FPGA-Verilog] traffic_lights

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] processor

[VHDL-FPGA-Verilog] ALUALUcontrol

[VHDL-FPGA-Verilog] 5

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

[VHDL-FPGA-Verilog] Designs

[VHDL-FPGA-Verilog] alu

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